Power-Aware Physical Design Strategies for Nanoscale VLSI Circuits Using Floorplanning, Placement, and Clock Tree Optimization

Rohit Banwarilal R

Authors

Rohit Banwarilal R Independent Researcher, India. Author

Keywords:

Nanoscale VLSI, Physical Design, Floorplanning, Placement Optimization, Clock Tree Synthesis, Low-Power Design, EDA Tools, Leakage Power, Dynamic Power, Semiconductor Technology

Abstract

With the continuous scaling of semiconductor technologies into the nanoscale regime, power consumption has become one of the most critical challenges in Very Large-Scale Integration (VLSI) circuit design. Physical design stages, including floorplanning, placement, and clock tree synthesis, significantly influence the overall power dissipation, timing performance, and reliability of integrated circuits. This paper reviews power-aware physical design strategies developed for reducing dynamic and leakage power in nanoscale VLSI systems. The study examines the impact of optimized floorplanning techniques, congestion-aware placement methodologies, and low-power clock tree optimization approaches on energy-efficient chip design. Furthermore, the paper discusses contemporary research trends, challenges, and future directions in physical design automation for advanced semiconductor technologies. The findings indicate that integrated power-aware optimization across multiple physical design stages can substantially reduce total power consumption while maintaining timing closure and design integrity.

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