Power-Aware Physical Design Strategies for Nanoscale VLSI Circuits Using Floorplanning, Placement, and Clock Tree Optimization. IJETTR [Internet]. 2026 Jul. 1 [cited 2026 Jul. 21];7(2):1-8. Available from: https://ijettr.com/index.php/IJETTR/article/view/IJETTR_07_02_001