“Power-Aware Physical Design Strategies for Nanoscale VLSI Circuits Using Floorplanning, Placement, and Clock Tree Optimization”, IJETTR, vol. 7, no. 2, pp. 1–8, Jul. 2026, Accessed: Jul. 21, 2026. [Online]. Available: https://ijettr.com/index.php/IJETTR/article/view/IJETTR_07_02_001