Power-Aware Physical Design Strategies for Nanoscale VLSI Circuits Using Floorplanning, Placement, and Clock Tree Optimization. INTERNATIONAL JOURNAL OF ENGINEERING TRENDS AND TECHNOLOGY RESEARCH (IJETTR), [S. l.], v. 7, n. 2, p. 1–8, 2026. Disponível em: https://ijettr.com/index.php/IJETTR/article/view/IJETTR_07_02_001. Acesso em: 21 jul. 2026.