Power-Aware Physical Design Strategies for Nanoscale VLSI Circuits Using Floorplanning, Placement, and Clock Tree Optimization. (2026). INTERNATIONAL JOURNAL OF ENGINEERING TRENDS AND TECHNOLOGY RESEARCH (IJETTR), 7(2), 1-8. https://ijettr.com/index.php/IJETTR/article/view/IJETTR_07_02_001